1. Field of the Invention
The present invention relates to a data processing apparatus and method for performing multi-cycle arbitration, and in particular for performing such arbitration between multiple access requests to be passed over a common access path shared by a plurality of resources.
2. Description of the Prior Art
In a data processing apparatus, it is often the case that a plurality of resources within the data processing apparatus share a common access path (also referred to herein as a shared access path). For example, multiple logic elements within the data processing apparatus, for example multiple master devices, may share access to memory consisting of one or more memory devices, with each of those memory devices comprising a plurality of memory banks. In this example, each bank of a memory device can be considered to be a shared resource. Typically, access to such memory is controlled by a memory controller, such that any access requests issued by the various logic elements seeking access to the memory will be received by the memory controller, typically the memory controller including a queue for buffering access requests prior to issuing them to the memory. Often, there is a single connection path between the memory controller and the memory, and accordingly this connection path forms a common access path to the plurality of banks contained within the memory.
As another example of a shared access path, many data processing apparatus provide interconnect circuitry for coupling the various master logic units and slave logic units provided within the apparatus, with the interconnect circuitry providing a plurality of connection paths over which communication between the master logic units and slave logic units can be established. Often, certain of the connection paths are shared between multiple logic units, as for example is typically the case in a single layer interconnect.
As another example of a shared access path, a number of peripheral devices may be connected to a peripheral bus. Often the peripheral bus will be connected to a main system bus via bridge circuitry, and any access requests destined for those peripheral devices will first be received by the bridge circuitry, which will then issue the access requests one at a time over the peripheral bus to the appropriate peripheral device. Since only one access request can be propagated-via the peripheral bus at any particular time, the peripheral bus forms a shared access path.
The above three examples of the occurrence of shared access paths within a data processing apparatus are provided merely by way of example, and are not intended to represent an exhaustive list of situations where shared access paths arise within a data processing apparatus.
Wherever such a shared access path exists, it will typically be necessary to provide arbitration circuitry for performing an arbitration operation to arbitrate between multiple access requests to be passed over that shared access path.
As the operating frequency of components of the data processing apparatus is increased, it becomes more and more difficult for the required arbitration operation to be performed in a single clock cycle. Accordingly, it is becoming necessary to provide arbitration circuitry that performs the arbitration operation as a multi-cycle operation. In order to achieve continuous throughput, arbitration of a subsequent access must begin before the outcome of the preceding arbitration operation is known. To achieve this, the arbitration circuitry can be provided with a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time.
However, often the resources sharing the common access path are such that they are unable to receive an access request every clock cycle. Indeed, once an access request has been granted access to a particular resource via the arbitration operation, the inter-access timing parameters associated with that resource may make that resource inaccessible for a number of clock cycles. Accordingly, it would be desirable to ensure that during that period the arbitration circuitry does not grant access to another access request seeking to access that particular shared resource.
However, when using the pipelined arbitration approach discussed above, multiple arbitration operations will typically be in progress at the same time, and hence for any particular arbitration operation in progress within the pipeline, it will not typically be possible to know the outcome of the one or more arbitration operations ahead of that particular arbitration operation in the pipeline at the time a decision needs to be made by that particular arbitration operation. Accordingly it is possible that multiple iterations of the arbitration operation in progress within the pipeline stages of the arbitration circuitry will grant access to access requests seeking to access the same shared resource. As a result, it is possible that an access request granted access by the arbitration circuitry may subsequently be stalled awaiting access to a shared resource, due to the above-mentioned inter-access timing parameter restrictions, and if this occurs this will clearly impact performance.
Accordingly, it would be desirable to provide an improved technique for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path, in situations where arbitration is performed as a multi-cycle operation.